This detects open pins (stuck behavior), shorts between nets (bridging), and solder ball bridging.
The goal is usually , meaning 99% of all possible stuck-at faults can be detected by the generated patterns. 5. The Economics of Testing
A Logic BIST controller is an on-chip hardware engine consisting of: digital systems testing and testable design solution
Chips do not live in isolation. They reside on printed circuit boards (PCBs), connected via microscopic traces, vias, and solder balls. Testing these interconnects—ensuring Chip A's pin is properly soldered to Chip B's pin—is the domain of , standardized as IEEE 1149.1 (commonly called JTAG, after the Joint Test Action Group that developed it).
To manage the infinite variety of physical defects, engineers use fault models. The most common is the Single Stuck-At (SSA) model, which assumes a signal line is permanently tied to logic 0 or logic 1. While simple, the SSA model effectively covers a high percentage of physical defects. Other models include the Bridging fault model for short circuits and the Delay fault model for timing-related failures. This detects open pins (stuck behavior), shorts between
Boundary scan solves board-level testing challenges. By placing a dedicated scan cell on every primary input and output pin of an IC, software can test the physical solder connections between different chips on a printed circuit board (PCB) without using physical test needles. This framework is governed by the Joint Test Action Group (JTAG) standard. Advanced Testing and Testable Design Trends
Test data volume for large SoCs can reach terabytes. Compression reduces this by 10x to 100x. The Economics of Testing A Logic BIST controller
: Minimizing dependencies between modules so that changes in one area do not unpredictably break another.
While Logic BIST is powerful, memories (SRAMs, DRAMs, ROMs, register files) are a special case. Embedded memories are the densest, most defect-prone structures on any chip. They also have a regular, predictable structure, making them ideal for a dedicated BIST solution.
Consider this statistic: For a complex System-on-Chip (SoC) manufactured on a 5nm process node, the cost of testing can account for 30% to 50% of the total manufacturing cost. If a defective chip escapes into the field—especially in automotive or medical applications—the cost of failure is not measured in dollars of repair, but in human lives.